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flash memory 1 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 document title 8m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to cha nge the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you have any questio ns, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 remark advance preliminary history initial issue. 1. i ol (r/ b ) of 1.8v device is changed. -min. value: 7ma -->3ma -typ. value: 8ma -->4ma 2. package part number is modified. k9f6408u0c-y ---> k9f6408u0c_t 3. ac parameter is changed. trp(min.) : 30ns --> 25ns 1. tbga package is changed. - 9mmx11mm 63ball tbga ---> 6mmx8.5mm 48ball tbga 2. part number(tbga package part number) is changed - k9f6408q0c-d ----> k9f6408q0c-b - k9f6408u0c-d -----> k9f6408u0c-b 3. k9f6408u0c-bcb0,bib0 products are added draft date jul. 24 . 2001 nov. 5 . 2001 nov. 12 . 2001 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.intl.samsungsemi.com/memory/flash/datasheets.html
flash memory 2 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 general description features voltage supply - 1.8v device(k9f6408q0c) : 1.65~1.95v - 3.3v device(k9f6408u0c) : 2.7 ~ 3.6 v organization - memory cell array : (8m + 256k)bit x 8bit - data register : (512 + 16)bit x8bit automatic program and erase - page program : (512 + 16)byte - block erase : (8k + 256)byte 528-byte page read operation - random access : 10 m s(max.) - serial page access - 1.8v device(k9f6408q0c) : 50ns - 3.3v device(k9f6408u0c) : 50ns fast write cycle time - program time - 1.8v device(k9f6408q0c) : 200 m s(typ.) - 3.3v device(k9f6408u0c) : 200 m s(typ.) - block erase time : 2ms(typ.) 8m x 8 bit bit nand flash memory command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation package - k9f6408u0c-tcb0/tib0 : 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) - k9f6408q0c-bcb0/bib0 48- ball tbga ( 6 x 8.5 /0.8mm pitch , width 1.0 mm) the k9f6408x0c is a 8m(8,388,608)x8bit nand flash memory with a spare 256k(262,144)x8bit. the device is offered in 1.8v or 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation pro- grams the 528-byte page in typical 200 m s and an erase operation can be performed in typical 2ms on an 8k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as c om- mand inputs. the on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. even the write-intensive systems can take advantage of the k9f6408x0c s extended reli- ability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. these algo- rithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ecc. the k9f6408x0c is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility. product list part number vcc range organization pkg type k9f6408q0c-b 1.65 ~ 1.95v x8 tbga k9f6408u0c-b 2.7 ~ 3.6v k9f6408u0c-t tsop ii
flash memory 3 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 pin configuration (tsop ii ) k9f6408u0c-tcb0/tib0 package dimensions v ss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c gnd r/ b re ce v cc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop ii - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )
flash memory 4 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 k9f6408x0c-bcb0/bib0 pin configuration (tbga) package dimensions wp ale we r/ b n.c re n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o 0 n.c n.c n.c v cc i/o 1 n.c v cc q i/o 5 v ss i/o 2 i/o 3 i/o 4 i/o 6 v ss 1 2 3 4 5 6 a b c d e f g h ce cle n.c n.c n.c i/o 7 6.00 0.10 6.00 0.10 ball #a1 side view top view 48-ball tbga (measured in millimeters) 0 . 3 5 0 . 0 5 0.45 0.05 6 5 4 3 2 1 c d e f g h bottom view a b 8 . 5 0 0 . 1 0 48- ? 0.45 0.05 0 . 8 0 x 7 = 5 . 6 0 0 . 8 0 8 . 5 0 0 . 1 0 0.80 x5= 4.00 0.80 0 . 9 0 0 . 1 0 0.08max b a 2 . 8 0 2.00 6.00 0.10 (datum b) (datum a) 0.20 m a b ?
flash memory 5 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 pin description pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vccq output buffer power v cc q is the power supply for output buffer. vccq is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. gnd gnd input for enabling spare area to do sequential read mode including spare area , connect this input pin to vss or set to static low state or to do sequential read mode excluding spare area , connect this input pin to vcc or set to static high state . dnu do not use leave it disconnected. note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected.
flash memory 6 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 512byte 16 byte figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 *l *l v cc x-buffers y-gating 64m + 2m bit command 2nd half page register & s/a nand flash array (512 + 16)byte x 16384 y-gating 1st half page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 22 a 0 - a 7 command ce re we cle wp i/0 0 i/0 7 v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 16k pages (=1,024 blocks) 512 byte 8 bit 16 byte 1 block =16 pages = (8k + 256) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 byte x 16 pages = (8k + 256) byte 1 device = 528 byte x 16pages x 1024 blocks = 66 mbits column address row address (page address) page register ale vcc/v cc q
flash memory 7 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 product introduction the k9f6408x0c is a 66mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data transf er between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 16 pa ges formed by one nand structures, totaling 4,224 nand structures of 16 cells. the array organization is shown in figure 2. the pro- gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1024 separately erasable 8k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9f64 08x0c. the k9f6408x0c has addresses multiplexed into 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. the 8m byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9f6408x0c. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. the 50h command is valid only when the gnd input(pin #40) is low level. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h (2) - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o
flash memory 8 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins and -0.2v on vcc and vccq pins. during transitions, this level may undershoo t to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v ccq +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit k9f6408q0c(1.8v) k9f6408u0c(3.3v) voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 v v cc q -0.2 to + 2.45 -0.6 to + 4.6 v temperature under bias k9f6408x0c-tcb0,bcb0 t bias -10 to + 125 c k9f6408x0c-tib0,bib0 -40 to + 125 storage temperature t stg -65 to + 150 c recommended operating conditions (voltage reference to gnd, k9f6408x0c-tcb0,bcb0:t a =0 to 70 c, k9f6408x0c-tib0,bib0:t a =-40 to 85 c) parameter symbol k9f6408q0c(1.8v) k9f6408u0c(3.3v) unit min typ. max min typ. max supply voltage v cc 1.65 1.8 1.95 2.7 3.3 3.6 v supply voltage v cc q 1.65 1.8 1.95 2.7 3.3 3.6 v supply voltage v ss 0 0 0 0 0 0 v dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions k9f6408q0c(1.8v) k9f6408u0c(3.3v) unit min typ max min typ max operat- ing current sequential read i cc 1 ce =v il, i out =0ma trc=50ns - 5 10 - 10 20 ma program i cc 2 - - 8 15 - 10 20 erase i cc 3 - - 8 15 - 10 20 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 input high voltage v ih i/o pins vccq-0.4 vccq +0.3 2.0 - v cc q+0.3 v except i/o pins v cc -0.4 - vcc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il - -0.3 - 0.4 -0.3 - 0.8 output high voltage level v oh k9f6408q0c :i oh =-100 m a k9f6408u0c :i oh =-400 m a v cc q-0.1 - - 2.4 - - output low voltage level v ol k9f6408q0c :i ol =100ua k9f6408u0c :i ol =2.1ma - - 0.1 - - 0.4 output low current(r/ b ) i ol (r/ b ) k9f6408q0c :v ol =0.1v k9f6408u0c :v ol =0.4v 3 4 - 8 10 - ma
flash memory 9 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by capacitance ( t a =25 c, v cc =1.8v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f6408x0c may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid block s is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bit s . do not erase or program factory-market bad blocks. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. parameter symbol min typ. max unit valid block number n vb 1014 1020 1024 blocks ac test condition (k9f6408x0c-tcb0,bcb0 :ta=0 to 70 c, k9f6408x0c-tib0,bib0:ta=-40 to 85 c k9f6408q0c : vcc=1.65v~1.95v , k9f6408u0c : vcc=2.7v~3.6v unless otherwise noted) parameter k9f6408q0c k9f6408u0c input pulse levels 0v to vccq 0.4v to 2.4v input rise and fall times 5ns 5ns input and output timing levels vccq/2 1.5v k9f6408q0c:output load (vccq:1.8v +/-10%) k9f6408u0c:output load (vccq:3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9f6408u0c:output load (vccq:3.3v +/-10%) - 1 ttl gate and cl=100pf program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms
flash memory 10 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol k9f6408q0c k9f6408u0c unit min max min max cle set-up time t cls 0 - 0 - ns cle hold time t clh 10 - 10 - ns ce setup time t cs 0 - 0 - ns ce hold time t ch 10 - 10 - ns we pulse width t wp 25 (1) - 25 (1) - ns ale setup time t als 0 - 0 - ns ale hold time t alh 10 - 10 - ns data setup time t ds 20 - 20 - ns data hold time t dh 10 - 10 - ns write cycle time t wc 50 - 50 - ns we high hold time t wh 15 - 15 - ns ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. 3. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol k9f6408q0c k9f6408u0c unit min max min max data transfer from cell to register t r - 10 - 10 m s ale to re delay( id read ) t ar1 20 - 20 - ns ale to re delay(read cycle) t ar2 50 - 50 - ns cle to re delay t clr 50 - 50 - ns ready to re low t rr 20 - 20 - ns re pulse width t rp 25 - 25 - ns we high to busy t wb - 100 - 100 ns read cycle time t rc 50 - 50 - ns ce access time t cea - 45 - 45 ns re access time t rea - 35 - 35 ns re high to output hi-z t rhz 15 30 15 30 ns ce high to output hi-z t chz - 20 - 20 ns re high hold time t reh 15 - 15 - ns output hi-z to re low t ir 0 - 0 - ns we high to re low t whr 60 - 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) - 5/10/500 (1) m s k9f6408u0c-y only last re high to busy (at sequential read) t rb - 100 - 100 ns ce high to ready(in case of inter- ception by ce at read) t cry - 50 +tr(r/ b ) (3) - 50 +tr(r/ b ) (3) ns ce high hold time(at the last serial read) (2) t ceh 100 - 100 - ns
flash memory 11 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nforma- tion regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same q uality level or as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perfor- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block of the nand flash, however, is fully guaranteed to be a valid block. nand flash technical notes all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd page of every invali d block has non-ffh data at the column address of 517. since the invalid block information is also erasable in most cases, it is impossi ble to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on t he original invalid block information and create the invalid block table via the following suggested flow chart(figure 1). any inte ntional erasure of the original invalid block information is prohibited. * figure 1. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table check "ffh" at the column address 517 of the 1st and 2nd page in the block
flash memory 12 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status registe write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 13 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the 1st ~ (n-1)th data to the same location of the block ?b?. * step4 do not further erase block ?a? by creating a ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~
flash memory 14 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effec - tive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be input- ted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting from ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~512), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9f6408u0c table 1. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 2. block diagram of pointer operation
flash memory 15 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 system interface using ce don?t-care. ce we t wp t ch timing requirements : if ce is is exerted high during data-loading, tcs must be minimum 10ns and twc must be increased accordingly. t cs start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. t cea out t rea ce re i/o 0 ~ 7 timing requirements : if ce is exerted high during sequential data-reading, the falling edge of ce to valid data(tcea) must be kept greater than 45ns. figure 3. program operation with ce don?t-care. figure 4. read operation with ce don?t-care. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re on k9f6408u0c_t, ce must be held low during tr
flash memory 16 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale i/o 0 ~ 7 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 22 t wp t ds t dh t alh
flash memory 17 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz* ? ? ? ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
flash memory 18 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t clr t clh t cs t wp t ch t ds t dh t rsto t ir t rhz* t chz* t whr t csto t cls read1 operation (read one page) notes : 1) is only valid on k9f6408u0c_t (tsop) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz dout 527 t rb t cry t wc ? ? ? 1) 1) on k9f6408u0c_t, ce must be held low during tr t ceh
flash memory 19 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 read1 operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar2 t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout dout 527 m address 511+m dout 511+m+1 t ar2 t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care ? ? selected row start address m 512 16 on k9f6408u0c_t, ce must be held low during tr on k9f6408u0c_t, ce must be held low during tr
flash memory 20 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 22 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc sequential row read operation (k9f6408u0c-t only) ce cle r/ b i/o 0 ~ 7 we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 22 dout n dout n+1 dout n+2 dout 527 dout 0 dout 1 dout 2 dout 527 busy m+1 output n ready ? ? ? ? ? ? ? ?
flash memory 21 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 block erase operation (erase one block) manufacture & device id read operation ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 22 a 9 ~ a 16 auto block erase erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc ? setup command ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech device t rea address. 1cycle t ar1 t clr device device code* k9f6408q0c 39h k9f6408u0c e6h code*
flash memory 22 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command regis- ter along with three address cycles. once the command is latched, it does not need to be written for the following page read ope ra- tion. three types of operations are available : random read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are transferred to the data registers in less than 10 m s(tr). the cpu can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address(column 511 or 527 depending on the state of gnd input pin). after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 10 m s again allows reading the selected page.the sequential row read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 t o 527 may be selectively accessed by writing the read2 command with gnd input pin low. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. unless the operation is aborted, the page address is automatically incre- mented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 command(00h/01h) is needed to move the pointer back to the main area. figures 3 through 6 show typical sequence and timings for each read operation. sequential row read is available only on k9f6408u0c_t : after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 1 0 m s again allows reading the selected page. the sequential row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 operation is allowed only within a block and after the last pa ge of a block is readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 5, 6 show typical sequence and timings for sequential row read oper - ation. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 22 data output(sequential) (00h command) 1st half array 2nd half array data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. ce cle ale r/ b we i/o 0 ~ 7 re t r on k9f6408u0c_t, ce must be held low during tr
flash memory 23 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 figure 5. sequential row read1 operation (k9f6408u0c-t only) figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 22 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field (gnd input =l, 00h command) 1st half array 2nd half array data field spare field 00h 01h a 0 ~ a 7 & a 9 ~ a 22 i/o 0 ~ 7 r/ b start add.(3cycle) start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) (a 4 ~ a 7 : don't care) 1st 2nd nth (gnd input =l, 01h command) 1st half array 2nd half array data field spare field 1st 2nd nth (gnd input =h, 00h command) 1st half array 2nd half array data field spare field 1st 2nd nth i/o 0 ~ 7 re t r t r t r t r ?
flash memory 24 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 figure 6. sequential row read2 operation (gnd input=fixed low) (k9f6408u0c-t only) page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data m ay be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the approp ri- ate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write controller automatically executes the algorithms and timings necessary for program and veri fy, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 7). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 22 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (16 byte) (16 byte) 1st half array 2nd half array data field spare field 1st 2nd nth (a 4 ~ a 7 : don t care) 1st figure 7. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 22 i/o 0 ~ 7 r/ b address & data input i/o 0 pass 528 byte data 10h 70h fail t r t r t r t prog ?
flash memory 25 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 figure 8. block erase operation block erase the erase operation is done on a block(8k byte) basis. block address loading is accomplished in two cycles initiated by an erase setup command(60h). only address a 13 to a 22 is valid while a 9 to a 12 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. wh en the erase operation is completed, the write status bit(i/o 0) may be checked. figure 8 details the sequence. 60h block add. : a 9 ~ a 22 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table2. read status register definition
flash memory 26 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code respectively. the command register remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h 00h ech device address. 1 cycle maker code device code t cea t ar1 trea figure 10. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase modes, the reset operation will abort these operation. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. internal address registers are cleared to "0"s and data regist ers to "1"s. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset command is not necessary for normal operation. refer to figure 10 below. after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b table3. device status t rst t clr device device code* k9f6408q0c 39h k9f6408u0c e6h code*
flash memory 27 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 11). its value c an be determined by the following guidance. v cc r/ b open drain output device gnd rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + s i l = 1.85v 3ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v figure 11. rp vs tr ,tf & rp vs ibusy
flash memory 28 k9f6408q0c : preliminary k9f6408u0c-bcb0,k9f6408u0c-bib0 k9f6408q0c-bcb0,k9f6408q0c-bib0 k9f6408u0c-tcb0,k9f6408u0c-tib0 the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.1v/2v(k9f6408q0c:1.1v, k9f6408u0c:2v). wp pin provides hardware pro- tection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences as shown in figure 12. the two step command sequence for program/erase provides additional software protection. figure 12. ac waveforms for power transition v cc wp high ? ? 1.8v device : ~ 1.5v we data protection & powerup sequence 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v ? 1 m s

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